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​劉仁傑

Jen-Chieh Liu

2012, Ph.D, National Central University (國立中央大學 電機博士)

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專長：數位/類比積體電路設計、時脈電路與低功率晶片設計

 

E-mail : jcliu@nuu.edu.tw 

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ROOM : B1-624                  TEL :  (037)38-2480

 

ResearchGate

 

Biography：

    Jen-Chieh Liu received the B.S. and M.S. degrees from the Department of Electronic Engineering, Fu-Jen Catholic University, Taipei, Taiwan, in 2004 and 2006, respectively. He received his Ph.D. from the Department of Electrical Engineering, National Central University, Taiwan, in 2012. He was with the Industrial Technology Research Institute, Taiwan, from 2010 to 2014.

     Since 2014, he has been with the National United University, where he is currently a Full Professor. His current research interests include low-power and high-speed clocking systems.

Profile

 - Experience

  • 115~迄今 「國立聯合大學-電機工程學系」教授。

  • 107~115 「國立聯合大學-電機工程學系」副教授。

  • 103~107 「國立聯合大學-電機工程學系」助理教授。

  • 101~迄今 「CIC國家晶片系統設計中心」晶片審查委員。

  • 99~103 「工業技術研究院-資訊與通訊研究所」工程師。

  • 101~103 「台北大學產業教師講座」講師。

  • 103 「TSIA短期培訓班- 微機電共振元件設計技術與應用」講師。

  • 97「中央大學超大型積體電路設計與實作」講師。

  • 96/94「台灣大學慶齡中心IC設計人才培訓班」電路佈局講師。

 - Research Area

  • PLL \ DLL \ All digital PLL

  • Crystal-less clock generator

  • Built-in jitter measurement circuits

  • Low power / low supply voltage clock synchronization systems

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Honors

  1. 「103年度智慧電子跨領域應用專題系列課程計畫」榮獲計畫類優等。

  2. 「102年度電腦與通訊期刊最佳論文獎」榮獲佳作論文獎。

  3. 「工研院102年傑出研究獎」榮獲工研精英金牌獎。

  4. 「工研院第十屆品質典範案例」榮獲產業科技研發類優勝佳作獎。

  5. 「國家晶片系統設計中心2011晶片製作」榮獲數位組優良設計獎。

  6. 「國家晶片系統設計中心2011晶片製作」榮獲類比組佳作設計獎。

  7. 「The 18th VLSI Design/CAD Symposium會議」榮獲最佳論文獎。

  8. 「國家晶片系統設計中心2007晶片製作」榮獲數位組優良設計獎。

  9. 「教育部94學年度SIP設計競賽」榮獲優等獎。

  10. 「教育部94學年度大學院校積體電路設計競賽」，榮獲研究所Full-custom組佳作獎。

  11. 「教育部92學年度大學院校積體電路設計競賽」，榮獲大學部Full-custom組優等獎。

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Publication List

- Journal Papers

  1. Jen-Chieh Liu*, Jun-Yu Chen, and Wen-Qi Liu, “A programmable delay chain for the source-synchronous interface,” Integr. - The VLSI Journal, vol. 105, 102517, pp. 1-14, Nov. 2025. (SCI)

  2. Jen-Chieh Liu* and Rui-Cheng Ai, “A low-voltage and low-power PLL for sub-GHz IoT applications,” Integr. - The VLSI Journal, vol. 103, 102424, pp. 1-11, Jul. 2025. (SCI)

  3. Jen-Chieh Liu*, Chi-Hua Chen, and Cheng-En Wu, “A high timing resolution and data rate pulse generator for automatic test equipment applications,” IEEE Trans. on Instrum. and Meas., vol. 74, no.4, pp.1-12, May 2025. (SCI)

  4. Jen-Chieh Liu*, Jian-Sheng Li, Yan-Xun Chen and Yu-Lung Lo, “A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application,” Microelectronics Journal, vol. 159, 106637, pp. 1-7, May 2025. (SCI)

  5. Jen-Chieh Liu* and Chuan Yang, “A digital delay locked loop with a monotonic delay line,” IEE Electronics Letters, vol. 59, no.11, pp. 1-3, Jun. 2023. (SCI)

  6. Hong-Yi Huang, Jen-Chieh Liu*, Fu-Chien Tsai, Kun-Hua Lee and Kun-Yuan Chen, “A 12-phase and 5-GHz PLL with a subfeedback loop technique,” Circuits, Systems, and Signal Processing, vol. 42, no.4, pp.1873-1892, Apr. 2023. (SCI)

  7. Jen-Chieh Liu* and Yan-Xun Chen, “DPLL-based VRO of time-to-digital converter,” IEEE Solid-State Circuits Letters, vol. 6, pp. 45-48, Feb. 2023. (ESCI)

  8. Yu-Lung Lo, Fang-Yu Fan, Hsi-Hua Wang, Yu-Hsin Li, Zi-Yi Chen, and Jen-Chieh Liu, “A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique,” Microsystem Technologies, vol. 27, no.4, pp.1335-1346, Apr. 2021. (SCI)

  9. Yu-Lung Lo, Yu-Hsin Li, Fang-Yu Fan, Chun-Yen Yu, and Jen-Chieh Liu*, “A low-jitter all-digital PLL with high-linearity DCO,” Microsystem Technologies, vol. 27, no.4, pp.1347-1357, April. 2021. (SCI)

  10. Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee and Jen-Chieh Liu*, “A power-saving adaptive equalizer with a digital-controlled self-slope detection,” IEEE Trans. on Circuits and Syst. I, vol. 65, no.7, pp. 2097-2108, July 2018. (SCI)

  11. Jen-Chieh Liu*, Chao-Jen Huang, and Pei-Ying Lee, “A high accuracy programmable pulse generator with a 10 ps timing resolution,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 26, no.4, pp. 621-629, Apr. 2018. (SCI)

  12. Yo-Hao Tu, Jen-Chieh Liu*, Kuo-Hsing Cheng, and Chih-Hsun Hsu, “A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs,” Analog Integrated Circuits and Signal Processing, vol. 93, no.10, pp.157-167, Oct. 2017. (SCI)

  13. Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu*, and Yu Lee, “A 8 phases 192 MHz crystal-less clock generator with PVT calibration,” IEICE Trans. on Electronics, E100-A (1), pp. 275-282, Jan. 2017. (SCI)

  14. Jen-Chieh Liu*, and Pei-Ying Lee, “A low power pulse generator for test platform applications,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E99-A (7), pp.1415-1416, Jul. 2016. (SCI)

  15. Yo-Hao Tu, Jen-Chieh Liu*, and Kuo-Hsing Cheng, “Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture,” IEICE Trans. on Electronics, E99-C (6), pp.655-658, Jan. 2016. (SCI)

  16. Yo-Hao Tu, Jen-Chieh Liu*, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu, “A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,” IEICE Electronics Express, vol. 13, no.2, pp.1-12, Jan. 2016. (SCI)

  17. Kuo-Hsing Cheng, Cheng-Liang Hung*, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, and Shi-Yang Sun, “A 0.9-8 GHz VCO with a differential active inductor for multistandard wireline SerDes,” IEEE Trans. on Circuits and Syst. II, vol. 61, no.8, pp.559-563, Ang. 2014. (SCI)

  18. Kuo-Hsing Cheng, Jen-Chieh Liu*, Hong-Yi Huang, and Yu-Tso Chen, “A wide supply voltage range and low-power all-digital clock generator,” Analog Integrated Circuits and Signal Processing, vol. 74, no.3, pp.517-526, Mar. 2013. (SCI)

  19. Kuo-Hsing Cheng, Jen-Chieh Liu*, and Hong-Yi Huang, “A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator,” IEEE Trans. on Circuits and Syst. II, vol.59, no.12, pp.888-892, Dec. 2012. (SCI)

  20. Hong-Yi Huang* and Jen-Chieh Liu, “All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator,” Analog Integrated Circuits and Signal Processing, vol. 68, no.3, pp.245-255, Sep. 2011. (SCI)

  21. Kuo-Hsing Cheng, Jen-Chieh Liu*, Hong-Yi Huang, Yu-Liang Li and Yong-Jhen Jhu, “A 6 GHz built-in jitter measurement circuit using multi-phase sampler,” IEEE Trans. on Circuits and Syst. II, vol.58, no.8, pp.492-496, Aug. 2011. (SCI)

  22. Kuo-Hsing Cheng, Jen-Chieh Liu*, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong, “Built-in jitter measurement circuit with calibration techniques for a 3-GHz clock generator,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol.19, no.8, pp.1325-1335, Aug. 2011. (SCI))

  23. Kuo-Hsing Cheng, Kai-Wei Hong*, Chi-Hsiang Chen, and Jen-Chieh Liu, “A high precision fast locking arbitrary duty cycle clock synchronization circuit,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol.19, no.7, pp.1218-1228, July 2011. (SCI)

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- International Conference Papers

  1. Wen-Hsuan Cheng, Bo-Jun Huang, and Jen-Chieh Liu, “A 0.5 V 2.4 GHz digital PLL with a sub-feedback loop technique,” International Conference on Artificial Intelligence, Computer, Data Sciences and Applications, pp. 1-5, Philippines, Feb. 2026.

  2. Yan-Ting Hsieh, Jen-Chieh Liu, Zhen Jie Hong, Kun-Ju Tsai, and Yu Lee, “Design of low-voltage PLL in a 16-nm FinFET CMOS process,” International Conference on Artificial Intelligence, Computer, Data Sciences and Applications, pp. 1-5, Philippines, Feb. 2026.

  3. Feng-Ming Wen, Wen-Dong Ke, Jen-Chieh Liu, Kun-Ju Tsai, and Yu Lee, “A low-voltage 10-MHz crystal-less clock generator,” International Conference on Solid State Devices and Materials, pp. 271-272, Japan, Sep. 2025.

  4. Cong-Ting Chen, Pei-Chun Hsieh, Jen-Chieh Liu, and Ching-Hua Chu, “A 2ps resolution timing generator for test platform,” International Conference on Solid State Devices and Materials, pp. 1021-1022, Japan, Sep. 2025.

  5. Yu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, and Jen-Chieh Liu, “A programmable DLL-based delay chain,” 21th International SoC Conference, pp. 29-30, Japan, Aug. 2024.

  6. Yu-Chun Hsiao, Rui-Cheng Ai, Zhen-Jie Hong, Yu-Lung Lo, and Jen-Chieh Liu, “A low-power PLL with a standby mode,” 21th International SoC Conference, pp. 23-24, Japan, Aug. 2024.

  7. Bo-Jun Huang, Wen-Yuan Tsai and Jen-Chieh Liu, “A 0.5-V 3-GHz digital PLL with a subfeedback loop technique,” 13th International Conference on Information and Electronics Engineering, South Korea, Feb. 2024.

  8. Rui-Cheng Ai, Zhe-yuan Jin and Jen-Chieh Liu, “Design of PLL with a power-down scheme,” 13th International Conference on Information and Electronics Engineering, South Korea, Feb.  2024.

  9. Wen-Dong Ke and Jen-Chieh Liu, “A crystal-less clock generator using a relaxation oscillator,” 13th International Conference on Information and Electronics Engineering, South Korea, Feb. 2024.

  10. Jen-Chieh Liu, Yu-Hsiang Tseng, and Wen-Yuan Tsai, “A boost DC-DC converter using PFM control scheme,” International Conference on Power and Energy Systems Engineering, pp. 1, Sep. 2019.

  11. Jian-Sheng Li and Jen-Chieh Liu, “A wide input range digital time-to-digital converter wireless network technology,” International Conference on Information and Electronics Engineering, pp. 37, Feb. 2019.

  12. Yu-Ping Li, Yu-Han Liu, and Jen-Chieh Liu, “An integer-N phase-locked loop with automatic VCO band selection,” International Conference on Information and Electronics Engineering, pp. 33, Feb. 2019.

  13. Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, and Hong-Yi Huang, “A chaotically injected timing technique for ring-based oscillators,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp. 1-4, Jun.  2016.

  14. Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching- Hsing Luo, and Jin-Chern Chiou, “PVT Insensitive high-resolution time to digital converter for intraocular pressure sensing” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp. 125-128, Apr. 2015.

  15. Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, and Hong-Yi Huang, “A radio-controlled receiver for clocks/watches and alarm applications,” IEEE International Symposium on Circuits and Systems, pp. 2672-2675, Jun. 2014.

  16. Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, and Kuo-Hsing Cheng, “A 64-MHz ~ 640-MHz 64-phase clock generator” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp. 51-54, Apr. 2014.

  17. Jen-Chieh Liu, Wei Chun Lee, Hong-Yi Huang, Kuo-Hsing Cheng, Chao-Jen Huang, Yu-Wei Liang, Jia-Hung Peng, and Yuan-Hua Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications” IEEE Asian Solid-state Circuits Conference, pp.117-120, Dec. 2012.

  18. Chih-Ping Cheng, Jen-Chieh Liu, and Kuo-Hsing Cheng, “Auto-calibration techniques in built-in jitter measurement circuit” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp.248-249, Apr. 2012.

  19. Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, and Ching-Hsing Luo, “All digital phase-locked loop using active inductor oscillator and novel locking algorithm,” IEEE International Symposium on Circuits and Systems, pp. 486-489, May 2011.

  20. Kuo-Hsing Cheng, Chih-Yu Chang, Jen-Chieh Liu, and Chih-Ping Cheng, “Measurement error analysis and calibration techniques for built-in jitter measurement circuit” IEEE International Symposium on VLSI Design Automation & Test, pp.1-4, Apr. 2011.

  21. Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, and Chien-Cheng Chen, “Loading effect insensitive an d high precision clock synchronization circuit” IEEE European Solid-State Circuits Conference, pp.514-517, Sep. 2010.

  22. Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, and Hong-Yi Huang, “A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp.285-288, Apr. 2010.

  23. Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang and Kuo-Hsing Cheng, “ 0.5 V 160-MHz 260 uW all digital phase-locked loop ” IEEE Symposium on Design and Diagnostics of Electronic Circuits and System, pp.186-193, Apr. 2009.

  24. Hong-Yi Huang, Jen-Chieh Liu, and Kuo-Hsing Cheng, “All digital PLL using pulse-based DCO” IEEE International Conference on Electronics, Circuits and Systems, pp.1268-1271 Dec. 2007.

  25. Hong-Yi Huang, Bo-Ruei Wang and Jen-Chieh Liu, “High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit,” IEEE International Symposium on Circuits and Systems, pp. 21-24, May 2006.

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- Patents

  1. 劉仁傑，張啟揚，涂祐豪，鄭國興，”非石英時脈產生器及其運作方法”中華民國，發明第 I 520495 B號，2016。

  2. Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, and Kuo-Hsing Cheng, “All digital crystal-less clock generator using temperature compensated techniques,” US Patent, , US 9,024,693, 2015.

  3. Hong-Yi Huang, Jen-Chieh Liu, and Yuan-Hua Chu, “High-resolution Varactors, Single-edge Triggered Digitally Controlled Oscillators, and All-digital Phase-locked Loops using the Same,” US Patent, US 8,125,286, 2012.

  4. Hong-Yi Huang, Jen-Chieh Liu, and Yuan-Hua Chu, “High-resolution Varactors, Single-edge Triggered Digitally Controlled Oscillators, and All-digital Phase-locked Loops using the Same,” US Patent, US 7,859,343, 2010.

  5. 黃弘一，劉仁傑，朱元華，”數位控制振盪器和全數位鎖相迴路” 中華人民共和國，專利號 ZL 2007 1 0088558.X，2011。

  6. 黃弘一，劉仁傑，朱元華，”數位控製變容器、數位控制振盪器和全數位鎖相迴路” 中華民國，發明第 I 348276，2011。

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- Local Papers

- Journal Papers

  1. Hong-Chao-Jen Huang and Jen-Chieh Liu “A high speed multi-phase switching DC-DC step-up     converter,” ICL Technical Journal, vol. 157, pp.88-93, Aug. 2014.

  2. Jen-Chieh Liu, Pei-Ying Lee, and Chao-Jen Huang, “A Multi-phase crystal-less clock generator with phase error corrector,” ICL Technical Journal, vol. 157, pp.80-87, Aug. 2014.

  3. Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng, and Pei-Ying Lee, “A 0.5 volt all-digital crystal-less clock generator using temperature techniques,” ICL Technical Journal,  vol. 153, pp.33-40, Dec. 2013.

  4. Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng, “An ultra-low voltage all digital phase-locked loop using a digital supply regulator,” ICL Technical Journal, vol. 150, pp.28-36, Apr. 2013.  

  5. Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng, “A 0.3 Volt All Digital Crystal-less Clock Generator,” ICL Technical Journal, vol. 143, no.2, pp.126-133, Feb. 2012.

 

- Conference Papers

  1. Jen-Chieh Liu*, Pei-Ying Lee, and Yu-Han Liu, “A ±60-ppm/℃ 600-MHz crystal-less clock generator using a phase error corrector,” The 26th VLSI Design/ CAD Symposium, Taiwan, Aug. 2015.

  2. Jen-Chieh Liu*, Pei-Ying Lee, and Yu-Ping Lee, “A 62 ps timing resolution arbitrary waveform generator for test platform applications,” The 26th VLSI Design/ CAD Symposium, Taiwan, Aug. 2015. (The Best Paper Nominee)

  3. Hong-Yi Huang, Fu-Chien Tsai, Jen-Chieh Liu, Kun-Yuan Chen and Ping-Che Hsieh,” Design and optimization of arbitrary stage ring oscillator using the interpolating scheme,” The 23th VLSI Design/CAD Symposium, Taiwan, Aug. 2012.

  4. Chih-Ping Cheng, Jen-Chieh Liu, and Kuo-Hsing Cheng,” Calibration techniques in multi-phase oscillator and time amplifier,” The 23th VLSI Design/CAD Symposium, Taiwan, Aug. 2012.

  5. Kuo-Hsing Cheng, Chih-Yu Chang, Jen-Chieh Liu,” Measurement Error analysis and calibration techniques for built-in jitter measurement circuit,” The 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010. (The Best Paper Nominee)

  6. Kuo-Hsing Cheng, Chih-Yu Chang, Jen-Chieh Liu, Shu-Yu Jiang and Yu-Tso Chen,” 3 GHz built-in jitter measurement circuit for a serial-Link transceiver,” The 20th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2009.

  7. Hong-Yi Huang and Jen-Chieh Liu,” All digital PLL using pulse-based DCO and bulk-controlled Varactor,” The 18th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2007. (The Best Paper)

  8. Hong-Yi Huang, Bo-Ruei Wang, and Jen-Chieh Liu,” High-gain and high-bandwidth rail-to-rail operational amplifier,” The 17th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2006.

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國立聯合大學第二(八甲)校區　電機工程學系　© MSIC 508 Lab

36063 苗栗市南勢里聯大2號 / 2, Lienda, Miaoli 36063, Taiwan, R.O.C
Room : B1-508　TEL : (037)-38-2481　統編：49502521　Design by : Y.P. Li 、 Y.H. Liu

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